Structure comprising tunable anti-reflective coating and method of forming thereof

ABSTRACT

An interconnect structure in back end of line (BEOL) applications comprising a tunable etch resistant anti-reflective (TERA) coating is described. The TERA coating can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The TERA coating can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

This application is a divisional of U.S. patent application Ser. No.10/706,968 filed Nov. 14, 2003. The entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure comprising a tunableanti-reflective coating (ARC) and a method of forming the structure and,more particularly, to a back-end of line (BEOL) structure comprising atunable ARC layer and a method of forming the structure.

2. Description of Related Art

In material processing methodologies, pattern etching comprises theapplication of a patterned mask of radiation-sensitive material, such asphotoresist, to a thin film on an upper surface of a substrate, andtransferring the mask pattern to the underlying thin film by etching.The patterning of the radiation-sensitive material generally involvescoating an upper surface of the substrate with a thin film ofradiation-sensitive material and then exposing the thin film ofradiation-sensitive material to a radiation source through a reticle(and associated optics) using, for example, a photolithography system.Then a developing process is performed, during which the removal of theirradiated regions of the radiation-sensitive material occurs (as in thecase of positive photoresist), or the removal of non-irradiated regionsoccurs (as in the case of negative resist) using a base developingsolution, or solvent. The remaining radiation-sensitive material exposesthe underlying substrate surface in a pattern that is ready to be etchedinto the surface. Photolithographic systems for performing theabove-described material processing methodologies have become a mainstayof semiconductor device patterning for the last three decades, and areexpected to continue in that role down to 65 nm resolution, and less.

The resolution (r_(o)) of a photolithographic system determines theminimum size of devices that can be made using the system. Having agiven lithographic constant k₁, the resolution is given by the equationr _(o) =k ₁ λ/NA,  (1)

-   -   where λ is the operational wavelength, and NA is the numerical        aperture given by the equation        NA=n·sin θ_(o).  (2)

Angle θ_(o) is the angular semi-aperture of the system, and n is theindex of refraction of the material filling the space between the systemand the substrate to be patterned.

Therefore, current lithographic trends involve increasing the numericalaperture (NA) in order to print smaller and smaller structures. However,although the increased NA permits greater resolution, the depth of focusfor the images projected into the light-sensitive material is reduced,leading to thinner mask layers. As the light-sensitive layer thicknessdecreases, the patterned light-sensitive layer becomes less effective asa mask for pattern etching, i.e., most of the (light-sensitive) masklayer is consumed during etching. Without a dramatic improvement in etchselectivity, single layer masks have become deficient in providing thenecessary lithographic and etch characteristics suitable for highresolution lithography.

An additional shortcoming of single layer masks is the control ofcritical dimension (CD). Substrate reflections at ultraviolet (UV) anddeep ultraviolet (DUV) wavelengths are known to cause standing waves inthe light-sensitive layer due to thin film interference. Thisinterference manifests as periodic variations in light intensity in thelight-sensitive layer during exposure resulting in vertically spacedstriations in the light-sensitive layer and loss of CD.

In order to counter the effects of standing waves in the light-sensitivelayer as well as provide a thicker mask for subsequent pattern etchtransfer, a bilayer or multilayer mask can be formed that incorporates abottom anti-reflective coating (BARC). The BARC layer comprises a thinabsorbing film to reduce thin film interference; however, the BARC layercan still suffer from several limitations including poor thicknessuniformity due in part to spin-on deposition techniques.

Alternatively, vapor deposited thin film ARC layers that offer theability to tune the optical properties of the film have been proposed toalleviate many of the above identified problems. Known as tunable etchresistant ARC (TERA) layers, TERA films can be produced having a tunableindex of refraction and extinction coefficient which can be optionallygraded along the film thickness to match the optical properties of thesubstrate with the imaging light-sensitive layer; see U.S. Pat. No.6,316,167, assigned to International Business Machines Corporation. Asdescribed in this patent, TERA films are used in lithographic structuresfor front end of line (FEOL) operations, such as gate formation, wherecontrol of the critical dimension is very important. However, thepresent inventors have recognized that TERA films have not been used inback end of line (BEOL) operations, such as metal interconnect, perhapsdue to the lesser importance of critical dimension to these operations.

SUMMARY OF THE INVENTION

One aspect of the present invention is to reduce or eliminate any or allof the above-described problems.

Another object of the present invention is to provide a structureincorporating a tunable anti-reflective coating, and a method of formingthe same.

According to another aspect, a semiconductor device is describedcomprising: a semiconductor substrate; a film stack formed on thesemiconductor substrate and including a tunable anti-reflective coatingformed within the film stack having a structural formula R:C:H:X,wherein R is selected from the group consisting of Si, Ge, B, Sn, Fe,Ti, and combinations thereof, and wherein X is not present or isselected from the group consisting of one or more of O, N, S, and F; anda damascene structure for a metal interconnect formed in the film stack.

According to another aspect, a process for forming an integrated circuitstructure is described comprising: forming a layer of dielectricmaterial on a substrate; forming a layer of tunable etch resistantanti-reflective (TERA) material on the layer of dielectric material; andforming a damascene structure for a metal interconnect by using thelayer of TERA material as at least one of a lithographic structure forthe formation of the interconnect structure, a hard mask, ananti-reflective coating, and a chemical mechanical polishing (CMP) stoplayer.

According to another aspect, a semiconductor device is describedcomprising: a semiconductor substrate; a film stack formed on thesemiconductor substrate; and means for integrating a tunableanti-reflective coating with a damascene structure for a metalinterconnect formed in the film stack.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A through 1H present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anembodiment of the present invention;

FIGS. 2A through 2F present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anotherembodiment of the present invention;

FIGS. 3A through 3F present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anotherembodiment of the present invention;

FIGS. 4A through 4J present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anotherembodiment of the present invention;

FIGS. 5A through 5D present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anotherembodiment of the present invention; and

FIGS. 6A through 6I present a simplified schematic representation of amethod of forming an interconnect structure in accordance with anotherembodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

As described above, a tunable etch resistant anti-reflective (TERA)coating can be integrated in front end of line (FEOL) applications, suchas the formation of a gate for transistor devices, wherein the TERAcoating provides substantial improvement to a lithographic structure forforming gate devices at the 65 nm device node and smaller. However,these films have not been used in back end of line (BEOL) operations,such as metal interconnect, perhaps due to the lesser importance ofcritical dimension to these operations. The present inventors haverecognized that use of TERA films as a tunable ARC layer as well as aremovable etch hard mask, a sacrificial layer, or chemical-mechanicalpolishing (CMP) stop layer provides useful properties for back end ofline (BEOL) operations, such as metal interconnect. According to thepresent invention, at least one TERA coating is integrated with a backend of line (BEOL) application, such as within a single damascene ordual damascene metal interconnect structure formed in a film stack,wherein at least one TERA coating provides at least one of alithographic structure for the formation of the interconnect structure,a hard mask, an anti-reflective coating, a sacrificial layer, or achemical mechanical polishing (CMP) stop layer.

Referring now to the drawings, wherein like reference numerals designateidentical or corresponding parts throughout the several views, FIGS. 1Athrough 1H present a schematic representation of a method of forming aninterconnect structure in a film stack according to one embodiment. Themethod can be characterized as the integration of a TERA coating into amultiple hard mask via first dual damascene structure. The term“via-first”, as used herein, refers to a process wherein an etchrelating to formation of the via occurs before an etch relating to theformation of another feature such as a trench.

As shown in FIG. 1A, the method begins with preparing a film stack 100comprising a substrate 110 having a metal line 112 formed therein, ametal cap layer 115 formed on the substrate 110, a first dielectriclayer 120 formed on the metal cap layer 115, an etch stop layer 125formed on the first dielectric layer 120, a second dielectric layer 130formed on the etch stop layer 125, a hard mask layer 135 formed on thesecond dielectric layer 130, a tunable etch resistant anti-reflective(TERA) coating 140 formed on the hard mask layer 135, and a layer oflight-sensitive material 145 formed on the TERA coating 140.

The film stack 100 may or may not include the hard mask layer 135. Whenfilm stack 100 includes hard mask layer 135, hard mask layer 135 canprovide at least one of a hard mask, or a CMP stop layer, and TERAcoating 140 can provide at least one of a top hard mask, a tunable ARClayer, a CMP stop layer, and a sacrificial layer when the hard masklayer 135 is utilized as CMP stop layer in a dual damascene structure.When film stack 100 does not include hard mask layer 135, TERA coating140 provides at least one of a single hard mask, a tunable ARC layer,and a CMP stop layer. The utilization of the TERA coating 140 as thelayer in contact with the light-sensitive material 145 of the film stack100 can facilitate control of the critical dimension (CD) of theinterconnect structure, or control of CD variation within theinterconnect structure (due to, for example, line edge roughness in thelayer of light-sensitive layer 145). The formation of the film stack 100can comprise steps, and utilize techniques known to those skilled in theart of preparing such (insulating) film stacks for inter-level, andintra-level, (metal) interconnect structures, such as single damasceneand dual damascene structures.

For example, the metal line 112 can comprise tungsten, aluminum, orcopper. Additionally, for example, the metal cap layer 115 can comprisea nitride or carbide material, such as silicon nitride (Si₃N₄) orsilicon carbide (SiC) or silicon carbonitride (SiCN) or siliconoxycarbonitride (SiCON), or combinations thereof, or other filmssuitable as a metal diffusion barrier. This layer can be formed usingmethods including but not limited to chemical vapor deposition (CVD), orplasma enhanced CVD (PECVD). Additionally, for example, the etch stoplayer 125, which can be an optional layer (as will be described later),can comprise a nitride material, such as silicon nitride (Si₃N₄), acarbide material, such as silicon carbide (SiC) or silicon oxycarbide(SiCO), or an oxide material such as silicon dioxide (SiO₂), orcombinations thereof. This layer can be formed using methods includingbut not limited to chemical vapor deposition (CVD), or plasma enhancedCVD (PECVD).

The first dielectric layer 120 and the second dielectric layer 130 cancomprise the same material composition, or different materialcomposition. Each dielectric layer can, for example, comprise silicondioxide, or a dielectric material having a nominal dielectric constantvalue less than the dielectric constant of SiO₂, which is approximately4 (e.g., the dielectric constant for thermal silicon dioxide can rangefrom 3.8 to 3.9). More specifically, the first and second dielectriclayers 120, 130 may have a dielectric constant of less than 3.7, or adielectric constant ranging from 1.6 to 3.7.

Each dielectric layer 120, 130 can be formed using chemical vapordeposition (CVD) or plasma enhanced chemical vapor deposition (PECVD)techniques, or spin-on dielectric (SOD) techniques such as those offeredin the Clean Track ACT 8 SOD and ACT 12 SOD coating systems commerciallyavailable from Tokyo Electron Limited (TEL). The Clean Track ACT 8 (200mm) and ACT 12 (300 mm) coating systems provide coat, bake, and curetools for SOD materials. The track system can be configured forprocessing substrate sizes of 100 mm, 200 mm, 300 mm, and greater. Othersystems and methods for forming a dielectric film on a substrate arewell known to those skilled in the art of both spin-on dielectrictechnology and CVD dielectric technology.

Furthermore, the first and second dielectric layers 120, 130 may, forexample, be characterized as low dielectric constant (or low-k)dielectric films. These dielectric layers may include at least one of anorganic, inorganic, and inorganic-organic hybrid material. Additionally,these dielectric layers may be porous or non-porous. For example, thesedielectric layers may include an inorganic, silicate-based material,such as carbon doped silicon oxide (or organo siloxane), deposited usingCVD techniques. Examples of such films include Black Diamond™ CVDorganosilicate glass (OSG) films commercially available from AppliedMaterials, Inc., or Coral™ CVD films commercially available fromNovellus Systems. Alternatively, these dielectric layers may includeporous inorganic-organic hybrid films comprised of a single-phase, suchas a silicon oxide-based matrix having CH₃ bonds that hinder fulldensification of the film during a curing or deposition process tocreate small voids (or pores). Still alternatively, these dielectriclayers may include porous inorganic-organic hybrid films comprised of atleast two phases, such as a carbon-doped silicon oxide-based matrixhaving pores of organic material (e.g., porogen) that is decomposed andevaporated during a curing process. Still alternatively, thesedielectric layers may include an inorganic, silicate-based material,such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ),deposited using SOD techniques. Examples of such films include FOx HSQcommercially available from Dow Corning, XLK porous HSQ commerciallyavailable from Dow Corning, and JSR LKD-5109 commercially available fromJSR Microelectronics. Still alternatively, these dielectric layers cancomprise an organic material deposited using SOD techniques. Examples ofsuch films include SiLK-I, SiLK-J, SiLK-H, SiLK-D, and porous SiLKsemiconductor dielectric resins commercially available from DowChemical, and GX-3™, and GX-3P™ semiconductor dielectric resinscommercially available from Honeywell.

Additionally, for example, the (optional) hard mask layer 135 cancomprise a nitride, such as silicon nitride (Si₃N₄), a carbide, such assilicon carbide (SiC) or silicon oxycarbide (SiCO), or a refractorymetal or refractory metal nitride such as tantalum nitride (TaN), orcombinations thereof. This layer may be formed employing methodsincluding but not limited to chemical vapor deposition (CVD) methods,plasma enhanced chemical vapor deposition (PECVD) methods and physicalvapor deposition (PVD) sputtering methods.

The TERA coating 140 comprises a structural formula R:C:H:X, wherein Ris selected from the group consisting of Si, Ge, B, Sn, Fe, Ti, andcombinations thereof, and wherein X is not present or is selected fromthe group consisting of one or more of O, N, S, and F. The TERA coating140 can be fabricated to demonstrate an optical range for index ofrefraction of approximately 1.40<n<2.60, and for extinction coefficientof approximately 0.01<k<0.78. Alternately, at least one of the index ofrefraction and the extinction can be graded (or varied) along athickness of the TERA coating 140. Additional details are provided inU.S. Pat. No. 6,316,167, entitled “Tunable vapor deposited materials asantireflective coatings, hardmasks and as combined antireflectivecoating/hardmasks and methods of fabrication thereof and applicationthereof, assigned to International Business Machines Corporation; theentire contents of which are incorporated herein in their entirety.Furthermore, the TERA coating 140 can be formed using PECVD, asdescribed in greater detail in pending US patent application, entitled“Method and apparatus for depositing materials with tunable opticalproperties and etching characteristics”, filed on Aug. 21, 2003; theentire contents of which are incorporated herein in their entirety. Theoptical properties of the TERA coating 140, such as the index ofrefraction, can be selected so as to substantially match the opticalproperties of the underlying layer, or layers. For example, underlyinglayers such as non-porous dielectric films can require achieving anindex of refraction in the range of 1.4<n<2.6; and underlying layerssuch as porous dielectric films can require achieving an index ofrefraction in the range of 1.2<n<2.6.

Additionally, for example, the layer of light-sensitive material 145 cancomprise photoresist, wherein a pattern can be formed therein usingmicro-lithography, followed by the removal of the irradiated regions ofthe light-sensitive material (as in the case of positive photoresist),or non-irradiated regions (as in the case of negative resist) using adeveloping solvent. For example, the layer (or layers) oflight-sensitive material 145 can be formed using a track system. Thetrack system can be configured for processing 248 nm resists, 193 nmresists, 157 nm resists, EUV resists, (top/bottom) anti-reflectivecoatings (TARC/BARC), and top coats. For example, the track system cancomprise a Clean Track ACT 8, or ACT 12 resist coating and developingsystem commercially available from Tokyo Electron Limited (TEL). Othersystems and methods for forming a photoresist film on a substrate arewell known to those skilled in the art of spin-on resist technology.Additionally, for example, the mask pattern can be formed using anysuitable conventional stepping lithographic system, or scanninglithographic system.

Once the layer of light-sensitive material 145 is formed on film stack100, it can be patterned with a first pattern 180 usingmicro-lithography, as described above. The first pattern 180 can, forexample, comprise a pattern for a via, or contact. As shown in FIG. 1B,the first pattern 180 can be transferred to the TERA coating using, forexample, dry plasma etching. The dry plasma etch process can comprise aplasma chemistry containing at least one of the species selected fromthe group consisting of oxygen, fluorine, chlorine, bromine, hydrogen,and combinations thereof. Alternatively, the plasma chemistry canfurther comprise nitrogen or an inert gas, such as a Noble gas (i.e.,helium, neon, argon, xenon, krypton, radon). Still alternatively, theplasma chemistry is chosen to exhibit high etch selectivity between theetch rate of the TERA coating and the etch rate of the overlyingpatterned layer of light-sensitive material. Still alternatively, theplasma chemistry is chosen to exhibit high etch selectivity between theetch rate of the TERA coating and the etch rate of the underlying hardmask layer. Once the first pattern 180 is transferred to the TERAcoating 140, the patterned TERA coating 140 can be utilized as a singlehard mask, or a top hard mask, when utilized with the hard mask stoplayer 135, for etching the underlying film stack. The remaininglight-sensitive material 145 is then removed using plasma or otherchemical techniques known to those skilled in the art.

Referring now to FIG. 1C, another layer of light-sensitive material 146is formed on film stack 100 using techniques described above. Therein, asecond pattern 190 is formed using micro-lithography. The second pattern190 can, for example, comprise a trench pattern. Once the second pattern190 is formed in the layer of light-sensitive material 146, the secondpattern 190 is transferred to the TERA coating 140, and the firstpattern 180 is transferred to the hard mask layer 135, as shown in FIG.1D. For example, the transfer of the second pattern and the firstpattern to the TERA coating and the hard mask layer, respectively, canbe performed simultaneously.

Following the pattern transfers to the TERA coating 140 and the hardmask layer 135, FIG. 1E illustrates the transfer of the first pattern180 to the second dielectric layer 130. Because the intermediate viaetch step of FIG. 1E is stopped at the etch stop layer 125, thestructure of FIG. 1E is referred to herein as a partial via structure.The transfer of the first pattern 180 to the second dielectric layer 130can comprise dry plasma etching, wherein the process is designed to stopon the underlying etch stop layer 125.

For instance, when etching oxide dielectric films such as silicon oxide,silicon dioxide, etc., or when etching inorganic low-k dielectric filmssuch as carbon doped silicon oxide materials, the etch gas compositiongenerally includes a fluorocarbon-based chemistry such as at least oneof C₄F₈, C₅F₈, C₃F₆, C₄F₆, CF₄, etc., and at least one of an inert gas,oxygen, or CO. Additionally, for example, when etching organic low-kdielectric films, the etch gas composition may include at least one of afluorocarbon gas, a nitrogen-containing gas, a hydrogen-containing gas,or an oxygen-containing gas. The techniques for selectively etching adielectric film, such as those described earlier, are well known tothose skilled in the art of dielectric etch processes. The plasmachemistry can be chosen to exhibit a high selectivity for etching thesecond dielectric layer 130 relative to the etch stop layer 125. Theetching processes can be chosen to exhibit any one of profile andcritical dimension (CD) control, etch uniformity (across the substrate),a flat etch front in order to avoid micro-trenching, etch selectivity tothe layer of light-sensitive material, and etch selectivity to the CMPstop layer and the etch stop layer.

Referring now to FIG. 1F, the first pattern 180 is transferred to theetch stop layer 125, and the second pattern 190 is transferred to thehard mask layer 135. For example, the transfer of the first pattern andthe second pattern to the etch stop layer and the hard mask layer,respectively, can be performed simultaneously. The pattern transfer canutilize dry plasma etching, wherein the plasma chemistry comprises atleast one of NF₃, SF₆, HBr, a fluorocarbon gas, a hydrofluorocarbon gas,or an oxygen-containing gas. The etching processes can be chosen toexhibit any one of profile and critical dimension (CD) control, etchselectivity to the layer of light-sensitive material, etch uniformity(across the substrate), and complete hard mask layer and etch stop layerremoval.

In FIG. 1G, the second pattern 190 is transferred to the seconddielectric layer 130, and the first pattern 180 is transferred to thefirst dielectric layer 120. For example, the transfer of the secondpattern and the first pattern to the second dielectric layer and thefirst dielectric layer, respectively, can be performed simultaneously,wherein the etching process for the second dielectric layer stops on theetch stop layer 125, and the etching process for the first dielectriclayer stops on the metal cap layer 115. The etching processes cancomprise dry plasma etching, utilizing plasma chemistries such as thosedescribed above for dielectric layers. The etching processes can bechosen to exhibit any one of profile and critical dimension (CD)control, etch uniformity (across the substrate), a flat etch front inorder to avoid micro-trenching, and first pattern/second pattern cornerselectivity. Any remaining light-sensitive material 146 may then beremoved using plasma or other chemical techniques known to those skilledin the art.

Thereafter, as shown in FIG. 1H, the first pattern 180 is transferred tothe metal cap layer 115, hence, completing the formation of, forexample, a via structure 155 and a trench structure 150.

According to another embodiment, FIGS. 2A through 2F present a schematicrepresentation of a method of forming an interconnect structure in afilm stack 200. The method can be characterized as the integration of aTERA coating into a full via first dual damascene structure. As usedherein, the term “full-via-first” refers to a process wherein an etchrelating to full formation of the via occurs before an etch relating tothe formation of another feature such as a trench. The film stack 200comprises a substrate 210 having a metal line 212 formed therein, ametal cap layer 215 formed on the substrate 210, a first dielectriclayer 220 formed on the metal cap layer 215, an etch stop layer 225formed on the first dielectric layer 220, a second dielectric layer 230formed on the etch stop layer 225, a hard mask layer 235 formed on thesecond dielectric layer 230, a tunable etch resistant anti-reflective(TERA) coating 240 formed on the hard mask layer 235, and a layer oflight-sensitive material 245 formed on the TERA coating 240, and it canbe prepared in much the same manner as the film stack 100 described inFIG. 1A. The film stack 200 may or may not include the hard mask layer235. When film stack 200 includes hard mask layer 235, hard mask layer235 can provide at least one of a hard mask, or a CMP stop layer, andthe TERA coating 240 can provide at least one of a top hard mask, atunable ARC layer, a CMP stop layer, and a sacrificial layer when thehard mask layer 235 is utilized as CMP stop layer in a dual damascenestructure. When film stack 200 does not include hard mask layer 235,TERA coating 240 provides at least one of a single hard mask, a tunableARC layer, and a CMP stop layer.

Once the layer of light-sensitive material 245 is formed on film stack200, it can be patterned with a first pattern 280 usingmicro-lithography, as described above. The first pattern 280 can, forexample, comprise a pattern for a via, or contact. As shown in FIG. 2B,the first pattern 280 can be transferred to the TERA coating 240, the(optional) hard mask layer 235, the second dielectric layer 230, theetch stop layer 225, and the first dielectric layer 220 using, forexample, dry plasma etching. The etching process for each layer cancomprise steps, and chemistries similar to those described above.Because the intermediate via etch step of FIG. 2B is stopped at themetal cap layer 215, the structure of FIG. 2B is referred to herein as afull via structure. Any remaining light-sensitive material 245 is thenremoved using plasma or other chemical techniques known to those skilledin the art.

Referring now to FIG. 2C, another layer of light-sensitive material 246is formed on film stack 200 using techniques described above. Therein, asecond pattern 290 is formed using micro-lithography. The second pattern290 can, for example, comprise a trench pattern. Once the second pattern290 is formed in the layer of light-sensitive material 246, the secondpattern 290 is transferred to the TERA coating 240, the hard mask layer235, and the second dielectric layer 230. Any remaining light-sensitivematerial 246 is then removed using plasma or other chemical techniquesknown to those skilled in the art. Thereafter, as shown in FIG. 2D, thefirst pattern 280 is transferred to the metal cap layer 215, hence,completing the formation of, for example, a via structure 250 and atrench structure 255.

It is possible that during the removal of the light-sensitive layer 245following the pattern transfer of the first pattern 280, the ashing (orstripping) process can affect the properties of TERA coating 240.Therefore, in one embodiment of the present invention, the TERA coating240 can be removed and re-deposited as shown in FIG. 2E. Thereafter, thepattern transfer of the second pattern 290 can be performed as shown inFIGS. 2C and 2D. However, during this etching process, the TERA coating240 may or may not be entirely removed from the exposed sidewalls of thefirst dielectric film 220. Therefore, in an alternate embodiment, asshown in FIG. 2F, the TERA coating 240 is removed following the firstpattern transfer, and a BARC layer material 270 is applied using, forexample, spin coating techniques. The BARC layer material 270 fillingvia structure 250 may then be partially removed or recessed using a dryplasma etch. The etch gas composition may include at least one of afluorocarbon gas, a nitrogen-containing gas, a hydrogen-containing gas,or an oxygen-containing gas. Thereafter, the pattern transfer of thesecond pattern 290 can be performed using standard techniques known tothose skilled in the art.

According to another embodiment, FIGS. 3A through 3F present a schematicrepresentation of a method of forming an interconnect structure in afilm stack 300. The method can be characterized as the integration of aTERA coating into a full via first dual damascene structure without astop layer. The film stack 300 comprises a substrate 310 having a metalline 312 formed therein, a metal cap layer 315 formed on the substrate310, a dielectric layer 320 formed on the metal cap layer 315, a tunableetch resistant anti-reflective (TERA) coating 340 formed on thedielectric layer 320, and a layer of light-sensitive material 345 formedon the TERA coating 340, and each layer in film stack 300 can beprepared in much the same manner as the film stack 100 described in FIG.1A. Herein, the TERA coating 340 can provide a CMP stop layer and atunable ARC layer.

Once the layer of light-sensitive material 345 is formed on film stack300, it can be patterned with a first pattern 380 usingmicro-lithography, as described above. The first pattern 380 can, forexample, comprise a pattern for a via, or contact. As shown in FIG. 3B,the first pattern 380 can be transferred to the TERA coating 340, andthe dielectric layer 320 using, for example, dry plasma etching. Theetching process for each layer can comprise steps, and chemistriessimilar to those described above. Any remaining light-sensitive material345 is then removed using plasma or other chemical techniques known tothose skilled in the art.

Referring now to FIG. 3C, another layer of light-sensitive material 346is formed on film stack 300 using techniques described above. Therein, asecond pattern 390 is formed using micro-lithography. The second pattern390 can, for example, comprise a trench pattern. Once the second pattern390 is formed in the layer of light-sensitive material 346, the secondpattern 390 is transferred to the TERA coating 340, and an upper portionof the dielectric layer 320. The depth to which the second pattern 390is transferred into the dielectric layer 320 can be adjusted bydecreasing, or increasing, the etch time during the etching process. Anyremaining light-sensitive material 346 is then removed using plasma orother chemical techniques known to those skilled in the art. Thereafter,as shown in FIG. 3D, the first pattern 380 is transferred to the metalcap layer 315, hence, completing the formation of, for example, a viastructure 350 and a trench structure 355.

As described above, it is possible that during the removal of thelight-sensitive layer 345 following the pattern transfer of the firstpattern 380, the ashing (or stripping) process can affect the propertiesof TERA coating 340. Therefore, in one embodiment, the TERA coating 340can be removed and re-deposited as shown in FIG. 3E. Thereafter, thepattern transfer of the second pattern 390 can be performed as shown inFIGS. 3C and 3D. During this etching process, however, the TERA coating340 may or may not be entirely removed from the exposed sidewalls of thedielectric layer 320. In an alternate embodiment, as shown in FIG. 3F,the TERA coating 340 is removed following the first pattern transfer,and a BARC layer 370 is applied using, for example, spin coatingtechniques. The BARC layer material 370 filling via structure 350 maythen be partially removed or recessed using a dry plasma etch. The etchgas composition may include at least one of a fluorocarbon gas, anitrogen-containing gas, a hydrogen-containing gas, or anoxygen-containing gas. Thereafter, the pattern transfer of the secondpattern 390 can be performed using standard techniques known to thoseskilled in the art.

According to yet another embodiment, FIGS. 4A through 4K present aschematic representation of a method of forming an interconnectstructure in a film stack 400. The method can be characterized as theintegration of a TERA coating into a multiple hard mask trench firstdual damascene structure. The film stack 400 comprises a substrate 410having a metal line 412 formed therein, a metal cap layer 415 formed onthe substrate 410, a first dielectric layer 420 formed on the metal caplayer 415, an (optional) etch stop layer 425 formed on the firstdielectric layer 420, a second dielectric layer 430 formed on the(optional) etch stop layer 425, an (optional) hard mask layer 435 formedon the second dielectric layer 430, a tunable etch resistantanti-reflective (TERA) coating 440 formed on the (optional) hard masklayer 435, a second TERA coating 441 formed on the first TERA coating440, and a layer of light-sensitive material 445 formed on the TERAcoating 441, and it can be prepared in much the same manner as the filmstack 100 described in FIG. 1A. The film stack 400 may or may notinclude the hard mask layer 435. When film stack 400 includes hard masklayer 435, hard mask layer 435 can provide at least one of a hard mask,or a CMP stop layer, and the second TERA coating 441 can provide atleast one of a top hard mask, a tunable ARC layer, a CMP stop layer, anda sacrificial layer when the hard mask layer 435 is utilized as CMP stoplayer in a dual damascene structure. When film stack 400 does notinclude hard mask layer 435, the second TERA coating 441 provides atleast one of a single hard mask, a tunable ARC layer, and a CMP stoplayer.

Once the layer of light-sensitive material 445 is formed on film stack400, it can be patterned with a first pattern 480 usingmicro-lithography, as described above. The first pattern 480 can, forexample, include a pattern for a trench. As shown in FIG. 4B, the firstpattern 480 can be transferred to the second TERA coating 441 using, forexample, dry plasma etching. The etching process can comprise steps, andchemistries similar to those described above. Any remaininglight-sensitive material 445 may then removed using plasma or otherchemical techniques known to those skilled in the art.

Referring now to FIG. 4C, another layer of light-sensitive material 446is formed on film stack 400 using techniques described above. Therein, asecond pattern 490 is formed using micro-lithography. The second pattern490 can, for example, comprise a via pattern. As shown in FIG. 4D, oncethe second pattern 490 is formed in the layer of light-sensitivematerial 445, the second pattern 490 is transferred to the first TERAcoating 440, and the (optional) hard mask layer 435.

Thereafter, as shown in FIG. 4E, the second pattern 490 is transferredto the second dielectric layer 430. Referring now to FIG. 4F, anyremaining light-sensitive material 446 is then removed using plasma orother chemical techniques known to those skilled in the art.

In FIG. 4G, the first pattern 480 is transferred to the first TERAcoating and the second pattern 490 is transferred to the (optional) etchstop layer 425. The transfer of the first pattern and the second patternto the first TERA coating and the (optional) etch stop layer,respectively, can be performed simultaneously, wherein the etchingprocess for the first TERA coating stops on the hard mask layer 435, andthe etching process for the (optional) etch stop layer stops on thefirst dielectric layer 420. The etching processes can comprise dryplasma etching, utilizing plasma chemistries such as those describedabove for dielectric layers. The etching processes can be chosen toexhibit any one of profile and critical dimension (CD) control, etchuniformity (across the substrate), a flat etch front in order to avoidmicro-trenching, and first pattern/second pattern corner selectivity.

Referring now to FIG. 4H, the first pattern 480 is transferred to thehard mask layer 435 and the second pattern 490 is partially transferredto the first dielectric layer 420. Thereafter, as shown in FIG. 41, thefirst pattern 480 is transferred to the second dielectric layer 430 andthe second pattern 490 is transferred to the first dielectric layer 420.The transfer of the first pattern and the second pattern to the seconddielectric layer and the first dielectric layer, respectively, can beperformed simultaneously, wherein the etching process for the seconddielectric layer stops on the etch stop layer 425, and the etchingprocess for the first dielectric layer stops on the metal cap layer 415.The etching processes can comprise dry plasma etching, utilizing plasmachemistries such as those described above for dielectric layers. Theetching processes can be chosen to exhibit any one of profile andcritical dimension (CD) control, etch uniformity (across the substrate),a flat etch front in order to avoid micro-trenching, and firstpattern/second pattern corner selectivity.

Thereafter, as shown in FIG. 4J, the second pattern 490 is transferredto the metal cap layer 415, hence, completing the formation of, forexample, a via structure 455 and a trench structure 450.

According to another embodiment, FIGS. 5A through 5D present a schematicrepresentation of a method of forming an interconnect structure in afilm stack 500. The method can be characterized as the integration of aTERA coating with a buried via mask dual damascene structure. The filmstack 500 comprises a substrate 510 having a metal line 512 formedtherein, a metal cap layer 515 formed on the substrate 510, a firstdielectric layer 520 formed on the metal cap layer 515, a first tunableetch resistant anti-reflective (TERA) coating 540 formed on the firstdielectric layer 520, and a layer of light-sensitive material 545 formedon the first TERA coating 540. Each layer can be prepared in much thesame manner as the film stack 100 described in FIG. 1A.

Once the layer of light-sensitive material 545 is formed on film stack500, it can be patterned with a first pattern 580 usingmicro-lithography, as described above. The first pattern 580 can, forexample, comprise a pattern for a via, or contact. As shown in FIG. 5B,the first pattern 580 can be transferred to the first TERA coating 540using, for example, dry plasma etching. The etching process for thefirst TERA layer can comprise steps, and chemistries similar to thosedescribed above. Following the etching process, the remaining layer oflight-sensitive material 545 is removed using plasma or other chemicaltechniques known to those skilled in the art.

Now referring to FIG. 5C, a second dielectric layer 530 is formed on thepatterned first TERA coating 540, a hard mask layer 535 is formed on thesecond dielectric layer 530, a second TERA coating 542 is formed on thehard mask layer 535, and another layer of light-sensitive material 546is formed on the second TERA coating 542. Each layer can be prepared inmuch the same manner as the film stack 100 described in FIG. 1A. Thefilm stack 500 may or may not include the hard mask layer 535. When filmstack 500 includes hard mask layer 535, hard mask layer 535 can provideat least one of a hard mask, or a CMP stop layer, and TERA coating 540can provide at least one of a top hard mask, a tunable ARC layer, a CMPstop layer, and a sacrificial layer when the hard mask layer 535 isutilized as CMP stop layer in a dual damascene structure. When filmstack 500 does not include hard mask layer 535, TERA coating 540provides at least one of a single hard mask, a tunable ARC layer, and aCMP stop layer.

Once the additional layer of light-sensitive material 546 is formed onfilm stack 500, a second pattern 590 is formed using micro-lithography.The second pattern 590 can, for example, comprise a pattern for atrench. As shown in FIG. 5D, once the second pattern 590 is formed inthe layer of light-sensitive material 546, the second pattern 590 istransferred to the second TERA coating 542, the (optional) hard masklayer 535, and the second dielectric layer 530 using, for example, dryplasma etching. While the first TERA coating 540 serves as an etch stoplayer, the first pattern 580 is transferred to the first dielectriclayer 520 using, for example, dry plasma etching. Any remaininglight-sensitive material 546 may then removed using plasma or otherchemical techniques known to those skilled in the art. Thereafter, themetal cap layer 515 can be removed, hence, completing the formation of,for example, a via structure 550 and a trench structure 555. The etchingprocesses for each layer can comprise steps, and chemistries similar tothose described above.

According to another embodiment, FIGS. 6A through 61 present a schematicrepresentation of a method of forming an interconnect structure in afilm stack 600. The method can be characterized as the integration of aTERA coating with single damascene structure. The film stack 600comprises a substrate 610 having a metal line 612 formed therein, ametal cap layer 615 formed on the substrate 610, a first dielectriclayer 620 formed on the metal cap layer 615, an (optional) first hardmask 625 formed on the first dielectric layer 620, a first TERA coating640 formed on the first (optional) hard mask 625, and a layer oflight-sensitive material 645 formed on the first TERA coating 640. Eachlayer can be prepared in much the same manner as the film stack 100described in FIG. 1A.

The film stack 600 may or may not include the hard mask layer 625. Whenfilm stack 600 includes hard mask layer 625, hard mask layer 625 canprovide at least one of a hard mask, or a CMP stop layer, and TERAcoating 640 can provide at least one of a top hard mask, a tunable ARClayer, and a CMP stop layer. When film stack 600 does not include hardmask layer 625, TERA coating 640 provides at least one of a single hardmask, a tunable ARC layer, and a CMP stop layer.

Once the layer of light-sensitive material 645 is formed on film stack600, it can be patterned with a first pattern 680 usingmicro-lithography, as described above. The first pattern 680 can, forexample, comprise a pattern for a via, or contact. As shown in FIG. 6B,the first pattern 680 can be transferred to the first TERA coating 640and the (optional) first hard mask 625 using, for example, dry plasmaetching. The etching process(es) can comprise steps, and chemistriessimilar to those described above. Thereafter, as shown in FIG. 6C, thefirst pattern 680 is transferred to the first dielectric layer 620using, for example, dry plasma etching. The etching process can comprisesteps, and chemistries similar to those described above. Following theetching process, as illustrated in FIG. 6D, the remaining layer oflight-sensitive material 645 is removed using plasma or other chemicaltechniques known to those skilled in the art.

Referring now to FIG. 6E, the first pattern 680 is transferred to themetal cap layer 615 using, for example, dry plasma etching. The etchingprocess can comprise steps, and chemistries similar to those describedabove.

Now referring to FIG. 6F, metal, such as aluminum or copper, isdeposited on film stack 600 to fill the first pattern (or via) in thefirst dielectric layer 620 using at least one of physical vapordeposition (PVD), CVD, PECVD, electro-plating, or any combinationthereof. Once the metal deposition is complete, the metal is polished,using, for example, CMP, to the first hard mask layer 625. Thereafter, asecond metal cap layer 626 is formed on the first (optional) hard masklayer 625 and metal-filled first pattern (or via) 613, a seconddielectric layer 630 is formed on the second metal cap layer 626, asecond (optional) hard mask layer 635 is formed on the second dielectriclayer 630, a second TERA coating 641 is formed on the second (optional)hard mask layer 635, and another layer of light-sensitive material 646is formed on the second TERA coating 641. Each layer can be prepared inmuch the same manner as the film stack 100 described in FIG. 1A. Thefilm stack 600 may or may not include the second hard mask layer 635.When film stack 600 includes hard mask layer 635, hard mask layer 635can provide at least one of a hard mask, or a CMP stop layer, and TERAcoating 641 can provide at least one of a top hard mask, a tunable ARClayer, and a CMP stop layer. When film stack 600 does not include hardmask layer 635, TERA coating 640 provides at least one of a single hardmask, a tunable ARC layer, and a CMP stop layer.

Once the additional layer of light-sensitive material 646 is formed onfilm stack 600, a second pattern 690 is formed using micro-lithography.The second pattern 690 can, for example, comprise a pattern for atrench. As shown in FIG. 6G, once the second pattern 690 is formed inthe layer of light-sensitive material 646, the second pattern 690 istransferred to the second TERA coating 641, the second (optional) hardmask layer 635, and the second dielectric layer 630 using, for example,dry plasma etching. As illustrated in FIG. 6H, any remaininglight-sensitive material 646 may then removed using plasma or otherchemical techniques known to those skilled in the art. Thereafter, thesecond metal cap layer 626 can be removed, hence, completing theformation of, for example, a via structure 650 (filled with metal) and atrench structure 655 (prepared for metal fill). The etching processesfor each layer can comprise steps, and chemistries similar to thosedescribed above.

Although only certain exemplary embodiments of this invention have beendescribed in detail above, those skilled in the art will readilyappreciate that many modifications are possible in the exemplaryembodiments without materially departing from the novel teachings andadvantages of this invention. Accordingly, all such modifications areintended to be included within the scope of this invention.

1. A semiconductor device comprising: a semiconductor substrate; a filmstack formed on the semiconductor substrate and including a tunableanti-reflective coating formed within said film stack having astructural formula R:C:H:X, wherein R is selected from the groupconsisting of Si, Ge, B, Sn, Fe, Ti, and combinations thereof, andwherein X is not present or is selected from the group consisting of oneor more of O, N, S, and F; and a damascene structure for a metalinterconnect formed in the film stack.
 2. The device of claim 1, whereinsaid tunable anti-reflective coating comprises a part of a lithographicstructure during the formation of said metal interconnect in said filmstack.
 3. The device of claim 1, wherein said tunable anti-reflectivecoating comprises a chemical mechanical polishing (CMP) stop layer forsaid damascene structure.
 4. The device of claim 1, wherein said tunableanti-reflective coating comprises at least one of a single hard mask, atop layer in a multiple layer hard mask, and an anti-reflective coating.5. The device of claim 1, wherein said tunable anti-reflective coatingis configured to have optical properties that substantially match theoptical properties of said film stack.
 6. The device of claim 5, whereinsaid optical properties comprise at least one of an index of refraction,and an extinction coefficient.
 7. The device of claim 6, wherein saidindex of refraction comprises a value ranging from 1.4 to 2.6.
 8. Thedevice of claim 6, wherein said extinction coefficient comprises a valueranging from 0.01 to 0.78.
 9. The device of claim 6, wherein at leastone of said index of refraction and said extinction coefficient isgraded along a thickness of said tunable anti-reflective coating. 10.The device of claim 6, wherein said index of refraction comprises avalue ranging from 1.2 to 2.6.
 11. The device of claim 1, wherein saidtunable anti-reflective coating comprises at least one of chemical vapordeposition (CVD) coating, and plasma enhanced CVD coating.
 12. Thedevice of claim 1, wherein said tunable anti-reflective coating isconfigured to provide at least one of control of a critical dimension ofsaid single damascene structure, and control of a critical dimensionvariation of said damascene structure.
 13. The semiconductor device ofclaim 1, wherein said damascene structure is a single damascenestructure.
 14. The semiconductor device of claim 1, wherein saiddamascene structure is a dual damascene structure.
 15. The semiconductordevice of claim 1, wherein said film stack further comprises a low-kdielectric layer. 16-27. (canceled)
 28. A semiconductor devicecomprising: a semiconductor substrate; a film stack formed on thesemiconductor substrate; and means for integrating a tunableanti-reflective coating with a damascene structure for a metalinterconnect formed in the film stack. 29-35. (canceled)